4.6 Article

Design and Control of Novel Single-Phase Multilevel Voltage Inverter Using MPC Controller

期刊

SUSTAINABILITY
卷 15, 期 1, 页码 -

出版社

MDPI
DOI: 10.3390/su15010860

关键词

voltage controller; multilevel inverter; SPWM; model predictive controller

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This article proposes a single-phase five-level voltage inverter topology with six switches for renewable energy applications. The suggested inverter reduces switching and conduction losses with its low switch count and uses a multi-error feedback controller with modified sinusoidal pulse width modulation to maintain the output voltage within the desired range. The absence of clamping diodes and bulky capacitors enables the use of a simple model predictive controller, decreasing circuit cost and improving overall efficiency. Simulation and hardware results are provided to validate the originality of the study.
In this article, a single-phase five-level voltage inverter topology with six switches is suggested for renewable energy applications. Control inverters that are low-cost, highly efficient, and resilient are required for modern renewable energy grids. The basic goal is to collect as much power as possible from the sources and feed the current into the grid with as little loss and harmonic distortion as possible. The suggested inverter's low switch count (six switches) with only two switches switched ON in a single state greatly decreases switching and conduction losses. Furthermore, a multi-error feedback controller with modified sinusoidal pulse width modulation (SPWM) is presented to manage the switching operation and maintain the output voltage in the appropriate range under different input and output voltage conditions. Furthermore, the lack of a clamping diode and bulky capacitors in the topology allows it to be controlled using a simple model predictive controller, lowering the cost of the circuit and improving the overall efficiency of the five-level inverter. Furthermore, for the variable input waveform, the total harmonic distortion (THD) evaluated by FFT analysis is within the allowed range of 1.8-4.5%. To validate the originality of this study, simulation and hardware results are provided and compared with current topologies.

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