Analysis and Design of a Non-Magnetic Bulk CMOS Passive Circulator Using 25% Duty-Cycle Clock

A circulator, which is a non-reciprocal device, is widely used in full-duplex systems, future communication and sensing networks, and quantum computing, and it is difficult to implement a passive topology on a chip. Based on switch-based spatio-temporal conductivity modulation, in this study, we design and implement a non-magnetic on-chip passive circulator operating at the Ku band in a 90-nm bulk CMOS technology using a 25% duty-cycle I/Q clock signal. With the virtue of the four-phase non-overlapping clock signal, the proposed circulator achieves a 3.9 dB transmitter (TX)-to-antenna (ANT) and a 4.0 dB ANT-to-receiver (RX) insertion loss with a 1-dB bandwidth of 2.7 GHz (21.4%). The TX-to-RX isolation is better than 17.2 dB, and the TX-to-ANT IIP3 and ANT-to-RX IIP3 are 19.7 dBm and 20.0 dBm, respectively, while occupying a die area of 1.55 mm x 1.15 mm. Although low-cost bulk CMOS technology is used, competitive isolation, linearity performance, and isolation bandwidth are achieved in the proposed design.

Automated summary

In this study, a non-magnetic on-chip passive circulator operating at the Ku band was designed and implemented using a 90-nm bulk CMOS technology. The proposed circulator achieved competitive isolation, linearity performance, and isolation bandwidth, with a 3.9 dB TX-to-ANT insertion loss and a 4.0 dB ANT-to-RX insertion loss.