期刊
ADVANCED OPTICAL MATERIALS
卷 -, 期 -, 页码 -出版社
WILEY-V C H VERLAG GMBH
DOI: 10.1002/adom.202201653
关键词
gate oxide passivation; high-performance photodetectors; interface traps; low-voltage field-effect transistors; MoS2 field-effect transistors
资金
- EU within FLAG-ERA JTC 2017 [NI 632/6-1, TU 149/9-1]
- Bavarian State Ministry of Science, Research and Arts through the grant Solar Technologies go Hybrid (SolTech)
- European Research Council Horizon 2020 through the ERC Grant Agreement PINNACLE [759744]
- Projekt DEAL
- Deutsche Forschungsgemeinsschaft (DFG) under Germany's Excellence Strategy [EXC 2089/1-390776260]
- Deutsche Forschungsgemeinschaft (DFG) [CRC 1375 NOA, SPP2244, TU149/13-1]
- DFG [TU149/16-1]
Adding an ultrathin coc passivation layer on the semiconductor/gate dielectric interface can reduce the interface trap density and enhance the electrical performance and photoresponsivity of MoS2 devices.
Trap states of the semiconductor/gate dielectric interface give rise to a pronounced subthreshold behavior in field-effect transistors (FETs) diminishing and masking intrinsic properties of 2D materials. To reduce the well-known detrimental effect of SiO2 surface traps, this work spin-coated an ultrathin (approximate to 5 nm) cyclic olefin copolymer (COC) layer onto the oxide and this hydrophobic layer acts as a surface passivator. The chemical resistance of COC allows to fabricate monolayer MoS2 FETs on SiO2 by standard cleanroom processes. This way, the interface trap density is lowered and stabilized almost fivefold, to around 5 x 10(11) cm(-2) eV(-1), which enables low-voltage FETs even on 300 nm thick SiO2. In addition to this superior electrical performance, the photoresponsivity of the MoS2 devices on passivated oxide is also enhanced by four orders of magnitude compared to nonpassivated MoS2 FETs. Under these conditions, negative photoconductivity and a photoresponsivity of 3 x 10(7) A W-1 is observed which is a new highest value for MoS2. These findings indicate that the ultrathin COC passivation of the gate dielectric enables to probe exciting properties of the atomically thin 2D semiconductor, rather than interface trap dominated effects.
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