期刊
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
卷 13, 期 1, 页码 26-33出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCPMT.2023.3234908
关键词
Finite element method simulation; micro-electro mechanical system (MEMS); multiphysics coupling; reliability simulation; thermal cycle simulation
This article investigates the reliability analysis of 3D CSP microelectro mechanical system (MEMS) and IC under thermal cycle impact coupled multiphysics loads. The mechanical behavior of the device is analyzed using COMSOL Multiphysics finite element software under a -55°C to 125°C thermal cycling and 1500 G at 1 ms with half-sine pulse impact coupled load. The study includes the analysis of thermal stress on single solder joint, whole device, and the simulation of device reliability under different magnitudes and forms of mechanical shock. The aim is to identify failure modes of interconnect structures including solder joints and the whole device for future design and optimize the layout of interconnect structures based on the stress distribution and deformation of the overall device.
In this article, reliability analysis of 3D CSP microelectro mechanical system (MEMS) and IC under thermal cycle impact coupled multiphysics loads was investigated. COMSOL Multiphysics, a finite element software, was used to analyze our device's mechanical behavior under a -55 C-?/125 C-? thermal cycling and 1500 G at 1 ms with half-sine pulse impact coupled load. In detail, MEMS chip was bonded on a silicon interposer by solder balls and an application specific integrated circuit (ASIC). Thermal stress of single solder joint, whole device, and the simulation of device reliability under different magnitudes and forms of mechanical shock were carried out, respectively. Combining the effects of impact and thermal stress loads, we hope to find out the failure modes of interconnect structures for future design including solder joints and whole device. The stress distribution and deformation of the overall device will be carried out for layout optimization of interconnect structures.
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