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Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

期刊

PROCEEDINGS OF THE IEEE
卷 111, 期 2, 页码 158-184

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JPROC.2023.3234607

关键词

Reliability; FeFETs; Hafnium oxide; Integrated circuit reliability; Nonvolatile memory; Random access memory; Ferroelectric materials; Ferroelectric FETs; reliability; endurance; retention; variability

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This article reviews the relevant literature on the reliability of doped hafnium oxide (HfO2) based ferroelectric transistors (FeFETs), focusing on the reliability physics of ferroelectric capacitors and the key reliability metrics of FeFETs. The integrative approach connects seemingly unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. The article concludes by proposing research opportunities for future development in this field.
Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, high-speed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field.

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