Impact of process-induced variability on multi-bit phase change memory devices

Phase change memory (PCM) shows great potential for multi-bit data storage for the next-generation non-vol-atile, high-speed, high-density memories. However, the process-induced variability poses a serious threat to the performance of multi-bit switching in nano-scale PCM devices. In this study, the impact of structural and interfacial parameters are studied systematically on the multi-level RESET programming of mushroom-type Ge2Sb2Te5 (GST) PCM devices by using TCAD simulations. Here, the impact of unintentionally varying struc-tural and interfacial input parameters is investigated for the optimized multi-bit PCM device of 60 nm heater diameter (HD) using the Plackett-Burman design of experiment. The quantitative analysis of input parameters shows that HD, GST thickness, and interfacial thermal resistance between GST and heater are the most sensitive parameters for the output parameter, RESET resistance (RRESET), while considering all the resistance levels from 1 to 7. Similarly, HD, heater height, and GST diameter are found to be the most governing parameters for RESET power (PRESET).

Automated summary

Phase change memory (PCM) shows great potential for the next-generation non-volatile, high-speed, high-density memories, but process-induced variability poses a serious threat to the performance of nano-scale PCM devices. In this study, the impact of structural and interfacial parameters on multi-level RESET programming of PCM devices was systematically investigated, and the most sensitive parameters for RESET resistance and power were identified.