4.8 Article

High Efficiency and High Power Density Partial Power Regulation Topology With Wide Input Range

期刊

IEEE TRANSACTIONS ON POWER ELECTRONICS
卷 38, 期 2, 页码 2074-2091

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2022.3207526

关键词

Topology; Rectifiers; Regulation; Zero voltage switching; Voltage control; Pulse width modulation; Bridge circuits; Dc transformer (DCX); high efficiency; high power density; partial power regulation; wide input range

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This article proposes a novel partial power regulation topology for data centers, which requires high-efficiency and high-power-density dc-dc converters with wide input range and galvanic isolation. The proposed topology achieves load power delivery through a three-ports LLC-based dc transformer regulated DCX. By introducing an appropriate negative current, the PWM achieves zero voltage switching. Furthermore, ultralow switching frequency can be achieved when the input voltage approaches the lower or upper limit, reducing switching losses and core losses.
Data centers require high efficiency and high power-density dc-dc converter with wide input range and galvanic isolation. To overcome the drawbacks of traditional single-stage LLC and two-stage solutions, a novel partial power regulation topology with wide input range is proposed in this article. The proposed topology delivers the load power through a three-ports LLC-based dc transformer regulated DCX (DCX). A pulsewidth modulation (PWM) converter is cascaded with one of the input ports of the DCX and then in series with the other input port to regulate the output voltage. Since a single transformer and a partial power PWMconverter are employed, high power density can be achieved. Furthermore, only a portion of the load power is transferred by the PWM converter, the efficiency sacrifice is reduced. By introducing an appropriate negative current, the zero voltage switching of the PWM is also achieved. Furthermore, when the input voltage approaches the lower or the upper limit, the switching frequency of the PWM regulator can be ultralow. As a result, switching losses and core losses are further reduced. Finally, a prototype with 190-475 V input and 12 V/500 W output is demonstrated, which achieves a peak efficiency of up to 97.2% and a power density of 153 W/in(3).

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