4.8 Article

An Encrypted On-Chip Power Supply With Random Parallel Power Injection and Charge Recycling Against Power/EM Side-Channel Attacks

期刊

IEEE TRANSACTIONS ON POWER ELECTRONICS
卷 38, 期 1, 页码 500-509

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2022.3206182

关键词

Charge recycling; encrypted on-chip power supply; hardware security; power/EM side-channel attack; random ON-time (ROT) modulation; random parallel power injection

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This article presents an encrypted on-chip power supply to protect crypto cores from power and electromagnetic (EM) side-channel attacks. It utilizes random parallel power injection and charge recycling to encrypt supply power activities, reducing power and performance overheads. The power supply maintains an uncorrelated input profile and attenuates EM leakage through spreading spectrum energy and increasing noise floor. A prototype IC with a 65nm CMOS process is fabricated, demonstrating improved power SCA immunity and meeting EM spectrum profile encryption standards. The power supply achieves high efficiency and minimal power overhead.
As hardware security becomes a crucial challenge for modern electronic devices to protect information privacy, this article presents an encrypted on-chip power supply to combat power and electromagnetic (EM) side-channel attacks (SCAs) for crypto cores. By splitting power and security into separate paths, random parallel power injection and charge recycling are realized to encrypt supply power activities for high SCA immunity while largely minimizing power and performance overheads. Despite of crypto core power variations, the proposed power supply can maintain uncorrelated input profile by adaptively modulating parallel noisy power injection. Moreover, its EM leakage is highly attenuated by spreading the spectrum energy to a wide frequency range and increasing noise floor. To achieve such, a recycled masking power stage with an encryption interface is designed to randomly inject power noise and recycle system charge with random ON-time modulation while still retaining nominal power delivery. A silicon IC prototype of this design is fabricated using a 65 nm CMOS process with an active die area of 0.19 mm(2). Measured input power profiles are fully encrypted to improve power SCA immunity. Operating at a nominal switching frequency of 10 MHz, random parallel power encryption reduces peak EM interference noise from 64.57 dB mu V to 43.12 dB mu V to meet EN55032 Class B standards and verify EM spectrum profile encryption. In response to a step-up load change from zero to full load current of 200 mA, the power supply achieves 1% settling time of 0.78 mu s, with measured voltage droop of 54 mV with no other performance overhead. It achieves a peak efficiency of 90.5%, only suffering the maximum power overhead of 4.9%.

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