期刊
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
卷 34, 期 1, 页码 262-274出版社
IEEE COMPUTER SOC
DOI: 10.1109/TPDS.2022.3217956
关键词
Chip multiprocessors; cache coherence; sparse directory; scalability
In this article, a scalable coherence directory, called tag-sharer-fusion (TSF) directory, is proposed. The TSF directory achieves low hardware complexity, high performance, and accuracy by optimizing directory entry format and tracking private and shared blocks. Simulation results demonstrate that the TSF directory outperforms state-of-the-art directory proposals in terms of storage overhead, performance, and network traffic.
In large-scale chip multiprocessors (CMPs), the scalability of a coherence directory becomes more important as the number of cores increases. However, previously proposed scalable coherence directories typically reduce the directory storage overhead at the cost of one or more aspects of performance, accuracy, and complexity. In this article, we propose the tag-sharer-fusion (TSF) directory, a scalable coherence directory with low hardware complexity, as well as with high performance and accuracy. Each directory entry has just enough bits to store a single sharer pointer and is divided into two primary formats: tag and sharer, where sharer entries store sharers but not tags. Each private block is tracked by a tag entry, and each shared block is tracked by a combination of a tag entry and a sharer entry in the same set. Simulation of a 128-core chip-multiprocessor with the PARSEC and SPLASH-2x benchmarks shows that the TSF directory requires only a quarter of the area of a non-scalable full-map sparse directory to achieve similar performance and network traffic, both with an average overhead within 1%. The TSF directory outperforms the state-of-the-art Pool and way-combining directory proposals in terms of storage overhead, performance, and network traffic.
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