Memory Window in Ferroelectric Field-Effect Transistors: Analytical Approach

A memory window (MW) of ferroelectric fieldeffect transistors (FeFETs), defined as a separation of the HIGH-state and the LOW-state threshold voltages, is an important measure of the FeFET memory characteristics. In this study, we theoretically investigate the relation between the FeFET MW and the P-E hysteresis loop of the ferroelectric gate insulator, and derive a compact model explicitly described by material parameters. It is found that the MW is linearly proportional to the ferroelectric polarization for the small polarization regime and converges to the limit value of 2 x coercive field x thickness when the remanent polarization is much larger than permittivity x coercive field. We discuss additional factors that possibly influence the MW in actual devices such as the existence of interlayer (no direct impact), interface charges (invalidity of linear superposition between the ferroelectric and charge trapping hysteresis), and minor-loop operation (behavior equivalent to the generation of interface charges).

Automated summary

This study investigates the relationship between the memory window (MW) of FeFETs and the P-E hysteresis loop of the ferroelectric gate insulator. A compact model is derived, and it is found that the MW is linearly proportional to the ferroelectric polarization. Additional factors such as interlayer existence, interface charges, and minor-loop operation are discussed.