Design and Characterization of n/p-well CMOS SPAD With Low Dark Count Rate and High Photon Detection Efficiency

have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18-mu m high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).

Automated summary

We propose a structure design for a single-photon avalanche diode fabricated in TSMC's 0.18-μm high-voltage CMOS technology. This design improves the limited operating excess voltage for an n-on-p type without any customized well layer. By introducing a deep p-well isolation layer, the excess bias is significantly increased, resulting in high photon detection probability (PDP) with low dark count rate. The n-on-p type device is suitable for a 3D-stacked backside illuminated structure and achieves high PDP at longer wavelengths. With improved jitter and after-pulsing probability, our designed device is suitable for light detection and ranging (LiDAR) applications.