Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory

In consumer electronics, 3-D NAND flash memory has become the state-of-the-art storage medium due to the multi-bit storage per cell and 3-D stacking technology. However, flash memory cells are commonly vulnerable to numerous types of circuit-level noise, resulting in threshold voltage distribution distortion and decreased reliability. Characterization of the threshold voltage distribution and modeling of optimal read reference voltages can help to mitigate the reliability deterioration. We provide a solution for improving the reliability of flash memories while reducing their implementation cost in this paper. The proposed pre-processing method is shown to yield a smaller number of scanning voltage steps reducing the time overhead and energy consumption of multiple read operations during the characterization of threshold voltage distributions. We propose a single state asynchronous estimation (SSAE) method to estimate optimal read reference voltages. Compared with the advanced two-state asynchronous estimation (TSAE) method, it is shown to reduce the computational and space overhead by half. Furthermore, compared with using the default read reference voltages, it is also shown to reduce RBER without exact knowledge of noise.

Automated summary

This paper proposes a solution to improve the reliability and reduce the cost of implementing flash memories. A pre-processing method is used to reduce the number of scanning voltage steps, reducing the time and energy consumption of multiple read operations. The proposed single state asynchronous estimation (SSAE) method is shown to reduce computational and space overhead compared to the two-state asynchronous estimation (TSAE) method, and it also reduces RBER without exact knowledge of noise.