DTC: A Drift-Tolerant Coding to Improve the Performance and Energy Efficiency of -Level-Cell Phase-Change Memory

Recently, phase-change memory (PCM) has emerged as a promising memory and storage technology. By storing multiple bits in a PCM cell, multi-level-cell (MLC) PCM further reduces the per-bit cost to improve its competitiveness. However, MLC PCM suffers from the high write latency and energy consumption caused by its complex write operations. Different from the existing works that attempt to improve the write latency and energy efficiency of the physical program & verify strategy for MLC PCM, we propose DTC, a drift-tolerant coding scheme, to apply fast write operation on MLC PCM without sacrificing the data accuracy. By exploiting the resistance drift and asymmetric write characteristics of PCM cells, the proposed DTC can significantly reduce the write latency and energy consumption of MLC PCM. Meanwhile, we propose a segmentation strategy to further improve the write performance with our coding scheme and an elimination methodology to avoid issuing unnecessary update operations. A series of analyses and experiments was conducted to evaluate the capability of the proposed scheme. It is encouraging that the proposed scheme can reduce 16.8%-32.1% energy consumption and 20.1%-32.6% write latency under the representative benchmarks, compared with the existing well-known schemes.

Automated summary

This study proposes a drift-tolerant coding scheme, DTC, for multi-level-cell phase-change memory (MLC PCM) to achieve fast write operations without sacrificing data accuracy. By exploiting resistance drift and asymmetric write characteristics of PCM cells, DTC significantly reduces write latency and energy consumption. Additionally, a segmentation strategy and an elimination methodology are introduced to further improve write performance.