期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
卷 69, 期 11, 页码 4233-4237出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2022.3188445
关键词
Decoding; Codes; Delays; Logic gates; Switches; Layout; Systematics; Digital-to-analog converter; splitting decoder; data transmission; spurious-free dynamic range; mismatch
资金
- National Natural Science Foundation of China [61674122, 62104193]
The article introduces a current-steering digital-to-analog converter (DAC) with 4-bit splitting + 8-bit binary segmented topology, which utilizes splitting decoding and DEM technique to optimize the performance of the DAC and improve the dynamic range.
This brief presents a current-steering digital-to-analog converter (DAC) with 4-bit splitting + 8-bit binary segmented topology. The proposed splitting decoding method can optimize the differential nonlinearity and output glitches of the DAC with a more simplified circuit scale than unary decoding. With a data-transmission topology, the splitting decoder has a low latency and accommodates fast synchronization control of current source switches. Moreover, the dynamic element matching (DEM) technique is used to suppress the harmonic distortion caused by the splitting current source mismatch. The DAC is designed using 0.18-mu m CMOS technology and occupies an area of 452.82 mu m x 491.76 mu m. With a 1.8 V analog supply and a 1.2 V digital supply, the DAC dissipates 12.2 mW at 500 MS/s. The spurious-free dynamic range of the DAC improves from 63.18 dB to 73.30 dB using DEM technique for an output signal of 8.30 MHz and by 8-10 dB within the Nyquist bandwidth.
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