期刊
IEEE MICRO
卷 42, 期 6, 页码 76-87出版社
IEEE COMPUTER SOC
DOI: 10.1109/MM.2022.3198321
关键词
Computer architecture; Nonvolatile memory; Computational modeling; Internet of Things; Pulse modulation; Microprocessors; Hardware; Edge computing; Hardware acceleration
资金
- European Union [780215]
This article discusses the importance of high energy efficiency in always-on TinyML perception tasks in IoT applications and proposes the use of analog compute-in-memory (CiM) with nonvolatile memory (NVM) to achieve this goal. The authors introduce AnalogNets model architectures and a comprehensive training methodology to maintain accuracy in the presence of analog nonidealities and low-precision data converters. They also present AON-CiM, a programmable phase-change memory (PCM) analog CiM accelerator, designed to reduce the complexity and cost of interconnects. Evaluation results show promising accuracy and efficiency for KWS and VWW tasks.
Always-on TinyML perception tasks in Internet of Things applications require very high energy efficiency. Analog compute-in-memory (CiM) using nonvolatile memory (NVM) promises high energy efficiency and self-contained on-chip model storage. However, analog CiM introduces new practical challenges, including conductance drift, read/write noise, fixed analog-to-digital (ADC) converter gain, etc. These must be addressed to achieve models that can be deployed on analog CiM with acceptable accuracy loss. This article describes AnalogNets: TinyML models for the popular always-on tasks of keyword spotting (KWS) and visual wake word (VWW). The model architectures are specifically designed for analog CiM, and we detail a comprehensive training methodology, to retain accuracy in the face of analog nonidealities, and low-precision data converters at inference time. We also describe AON-CiM, a programmable, minimal-area phase-change memory (PCM) analog CiM accelerator, with a layer-serial approach to remove the cost of complex interconnects associated with a fully pipelined design. We evaluate the AnalogNets on a calibrated simulator, as well as real hardware, and find that accuracy degradation is limited to 0.8%/1.2% after 24 h of PCM drift (8 bits) for KWS/VWW. AnalogNets running on the 14-nm AON-CiM accelerator demonstrate 8.55/26.55/56.67 and 4.34/12.64/25.2 TOPS/W for KWS and VWWs with 8-/6-/4-bit activations, respectively.
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