相关参考文献
注意:仅列出部分参考文献,下载原文获取全部文献信息。Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
Luca Bertulessi et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2022)
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors
Rongjin Xu et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2022)
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector
Suneui Park et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2022)
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
Seyeon Yoo et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2021)
A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth
Xuefan Jin et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2020)
A 0.0056-mm2-249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs
Shiheng Yang et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers
Karim M. Megawer et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114
Seojin Choi et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler
Ahmed Elkholy et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
A General Theory of Injection Locking and Pulling in Electrical Oscillators-Part I: Time-Synchronous Modeling and Injection Waveform Design
Brian Hong et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops
Alessio Santiccioli et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2019)
A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth
Xuefan Jin et al.
2019 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) (2019)
A 0.4-ps-Jitter-52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD
Bangan Liu et al.
IEEE SOLID-STATE CIRCUITS LETTERS (2019)
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique
Hyunik Kim et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2017)
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors
Hao Xu et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2017)
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector
Seojin Choi et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2016)
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells
Mina Kim et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2016)
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
Salvatore Levantino et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2015)
A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications
Clement Jany et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2015)
A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth
Chih-Lu Wei et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2015)
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops
Amr Elshazly et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2013)
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
Xiang Gao et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2010)
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2
Xiang Gao et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2009)
Noise Analysis and Minimization in Bang-Bang Digital PLLs
Marco Zanuso et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2009)
A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance
Bela M. Helal et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2008)