期刊
IEEE ELECTRON DEVICE LETTERS
卷 44, 期 2, 页码 197-200出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2022.3229763
关键词
Stress; Silicon; Field effect transistors; Logic gates; Hot carriers; Degradation; Tunneling; Border traps; forksheet FETs; hot-carriers; non-equilibrium BTI; non-radiative multiphonon model
We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress and find that the charge trapping occurs above and below the horizontal projection of the sheet. The charge profile is independent of the sheet width, and the trapping in the forksheet FET wall is significantly smaller than the trapping in the gate stack.
We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress by calculating carrier distribution functions and using a non-radiative multiphonon model. We observe charge trapping above and below the horizontal projection of the sheet in the wall. We find the charge profile not to depend on the sheet width and the trapping in the forksheet FET wall to be significantly smaller than the trapping in the gate stack.
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