4.6 Article

Scheme for Multi-Chiplet Integration With Low Thermal Budget by Asymmetric Cu-Cu Bonding With Au Passivation Bonding Structure

期刊

IEEE ELECTRON DEVICE LETTERS
卷 44, 期 3, 页码 492-495

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2023.3239011

关键词

Passivation; Bonding; Periodic structures; Heating systems; Gold; Reliability; Substrates; 3D integration; chiplet; Cu~bonding; passivation structure

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This study proposes a multi-chiplet integration scheme by utilizing Cu-Cu bonding with low thermal budget and an asymmetric passivation bonding structure. The single-sided passivation structure is achieved through one-sided heating thermal compression bonding at 150°C, enhancing bonding quality with a small grain size passivation layer. Transmission electron microscope analysis of the bonding interface of the single-sided passivation structure and its corresponding mechanism is inferred. Compared to the original passivation structures, the single-sided passivation structure not only enhances bonding quality but also provides higher bonding strength with lower contact resistance than Cu-Cu direct bonding, making it applicable for multi-chiplet integration.
This study proposed a multi-chiplet integration scheme using Cu-Cu bonding with a low thermal budget by utilizing an asymmetric passivation bonding structure. The single-sided passivation structure was achieved through one-sided heating thermal compression bonding at 150 C-?; the bonding quality was enhanced by the passivation layer with small grain size. The bonding interface of the single-sided passivation structure was analyzed through transmission electron microscope, and the corresponding mechanism was inferred. Compared with original passivation structures, the single-sided passivation structure not only enhanced bonding quality but also provided higher bonding strength, and the contact resistance was lower than Cu-Cu direct bonding. Therefore, the single-sided passivation structure with low thermal budget, high bonding strength and high throughput can be applied to multi-chiplet integration.

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