Estimation of interfacial-layer thickness from voltage-dependent domain switching times in LiNbO3 single-crystal domain wall memory

- Conducting domain walls created through the local domain 180 degrees reversal within LiNbO3 mesa-like cells fabricated at the surface of a single-crystal LiNbO3 thin film have enabled ferroelectric domain wall memories, transistors, and sensors, where volatile switching in the do-mains within the interfacial layers near two side electrodes can rectify diode-like wall conduction under an applied voltage higher than an onset voltage. The diodes at interfaces not only can per -form NOT, NAND, and NOR gate logic functions for in-memory computing, but can also work as embedded selectors for the fabrication of crossbar arrays of the memories in adjustable onset voltages that are proportional to the thicknesses of interfacial layers. Here, we develop a method to estimate the interfacial-layer thickness through the measurements of voltage-dependent domain switching times across two interfacial layers and an entire memory cell, respectively. Both depen-dences can be fitted according to the Merz law using an identical activation field from which we derived the equivalent electrical thickness of the interfacial layer. This non-destructive estimation paves the way to tailoring onset voltages of the diodes through the regulation of interfacial-layer thicknesses within various domain wall nanodevices.

Automated summary

Conducting domain walls created through the local domain 180 degrees reversal within LiNbO3 mesa-like cells fabricated at the surface of a single-crystal LiNbO3 thin film have enabled the development of ferroelectric domain wall memories, transistors, and sensors. The diodes at interfaces not only can perform logical functions for in-memory computing, but can also work as embedded selectors for the fabrication of crossbar arrays of the memories. A non-destructive estimation method has been developed to tailor the onset voltages of the diodes through the regulation of interfacial-layer thicknesses within various domain wall nanodevices.