A high speed pseudo-random bit generator driven by 2D-discrete hyperchaos

Pseudo-Random Number Generators (PRNGs) yielding numbers with high rates and good randomness quality are crucial for security as networks expand in an ever-connected way. In this work, firstly, we construct a new 2D discrete hyper-chaotic map with linear cross-coupled topological structure combined with the Tent and Logistic map. The proposed map with the aforementioned structure enables it to outperform other enhanced chaotic maps developed recently. Secondly, an efficient PRNG based on the proposed one is implemented on the field-programmable gate array (FPGA) Xilinx xc7k325tffg900-2. Compared with those typical PRNGs, the sequences generated by ours own a high level of randomness and passed the well-known TestU01, Dieharder, and the National Institute of Standards and Technology (NIST) SP800-22 test suite successfully without post -processing. Experimental results show that the proposed PRNG occupies merely 1.4 percent of the resources available on the targeted FPGA despite it yielding numbers with a large bit depth. In addition, the timing report shows the system can operate effectively at a clock of 158 MHz with a maximum throughput of 9.26 Gbps which outperforms the state-of-the-art.

Automated summary

In this work, a new 2D discrete hyper-chaotic map with linear cross-coupled topological structure combined with the Tent and Logistic map is constructed, outperforming other enhanced chaotic maps developed recently. An efficient PRNG based on the proposed map is then implemented on FPGA, generating sequences with high randomness and passing various tests successfully. Experimental results show that the proposed PRNG occupies only 1.4% of the available FPGA resources, while achieving a clock frequency of 158 MHz with a maximum throughput of 9.26 Gbps, outperforming the state-of-the-art.