Mechanisms of instability retention for ferroelectric field effect transistors with HfZrO2 gate stack scaling down

Instability threshold voltage (V-T) with retention loss of read-after-write is a critical issue with fundamental physics for ferroelectric field effect transistors (FeFETs) scaling down under high-speed operation. The mechanisms including charge trapping and depolarization field (E-dep) are discovered and related to surface potential and coercive field (E-C). The trapped charge can be effectively detrapped by opposite polarity stimulation and validated by technology computer-aided design modeling. In addition, the E-dep is revealed to be serious with ferroelectric HfZrO2 (FE-HZO) thin-down due to the unstable low-V-T state at a gate voltage (V-G) of 0 V. The tunable base voltage (V-base) compensates the E-dep-based polarization degradation. A stable low-V-T read-after-write for a 5-nm-thick HZO FeFET is experimentally demonstrated by the opposite polarity detrapping scheme hybrid with a V-base optimization simultaneously for a wide range of delay times from 10(-7) to 10(2) s. This result provides the feasibility for scaling down FeFETs for nonvolatile memory applications in the future. Published under an exclusive license by AIP Publishing.

Automated summary

This study investigates the instability threshold voltage (V-T) and retention loss of read-after-write in ferroelectric field effect transistors (FeFETs) under high-speed operation. The mechanisms of charge trapping and depolarization field (E-dep) are discovered and related to surface potential and coercive field (E-C). Trapped charge can be effectively detrapped by opposite polarity stimulation and validated through technology computer-aided design modeling. In addition, the study reveals that E-dep becomes severe with ferroelectric HfZrO2 (FE-HZO) thinning due to unstable low-V-T state at a gate voltage (V-G) of 0 V. The utilization of tunable base voltage (V-base) compensates for E-dep-based polarization degradation, and a stable low-V-T read-after-write is experimentally demonstrated for a 5-nm-thick HZO FeFET by the opposite polarity detrapping scheme hybrid with simultaneous V-base optimization. This research result provides the feasibility for scaling down FeFETs for future nonvolatile memory applications.