Threshold voltage instability by charge trapping effects in the gate region of p-GaN HEMTs

In this work, threshold voltage instability of normally off p-GaN high electron mobility transistors has been investigated by monitoring the gate current density during a device on-state. The origin of gate current variations under stress has been ascribed to charge trapping occurring at different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (V-G < 6 V) or holes (V-G > 6 V) are trapped, causing a positive or negative threshold voltage shift delta V-TH, respectively. By monitoring the gate current variations at different temperatures, activation energies associated with the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated with the creation of crystallographic dislocation-like defects extending across different interfaces (p-GaN/AlGaN/GaN) of the gate stack. (C) 2022 Author(s)

Automated summary

This work investigates the threshold voltage instability of normally off p-GaN high electron mobility transistors by monitoring the gate current density during device on-state. It is found that the gate current variations are caused by charge trapping at different interfaces in the metal/p-GaN/AlGaN/GaN system. Depending on the stress bias level, trapped electrons or holes lead to positive or negative threshold voltage shift, respectively.