Significant improvement of endurance of Si FeFET through minor hysteresis loop and narrow write pulse width

The HfO2-based Si ferroelectric field-effect transistor has been proposed as an emerging memory device due to its low write power, high speed, CMOS compatibility, and scalability. While the poor endurance limits its application, which is attributed to charge trapping and defect generation. In this work, we investigate the effect of the minor loop operation on defect generation. We find that using a minor loop operation, the trap generation is suppressed, which is quantitively extracted by the low-frequency noise method. We get the endurance of 6 x 10(7) cycles for Si FeFET with a Hf0.5Zr0.5O2 ferroelectric layer through minor hysteresis loop operation.

Automated summary

The HfO2-based Si ferroelectric field-effect transistor shows promise as an emerging memory device due to its low power consumption, high speed, compatibility with CMOS, and scalability. In this study, we explore the effect of minor loop operation on defect generation and find that it can effectively suppress trap generation, increasing the device's endurance.