4.8 Article

Synthesis of Oxide Interface-Based Two-Dimensional Electron Gas on Si

期刊

ACS APPLIED MATERIALS & INTERFACES
卷 14, 期 47, 页码 53442-53449

出版社

AMER CHEMICAL SOC
DOI: 10.1021/acsami.2c18934

关键词

two-dimensional electron gas; perovskite oxide membranes; SrTiO3; Si wafer; molecular beam epitaxy

资金

  1. National Key R&D Program of China
  2. National Natural Science Foundation of China
  3. Natural Science Foundation of Jiangsu Province
  4. 333 High Level Talent Training Project of Jiangsu Province
  5. Fundamental Research Funds for the Central Universities
  6. [2018 YFA 0 3 0 5 8 0 0]
  7. [2019YFB2205402]
  8. [2021YFA1400400]
  9. [51772145]
  10. [11861161004]
  11. [BK20180003]
  12. [0213-14380221]

向作者/读者索取更多资源

Conductive amorphous Al2O3/SrTiO3 heterostructures have been successfully synthesized on a silicon wafer through a growth-and-transfer method. The formation of a two-dimensional electron gas (2DEG) at the interface of aAO/STO has been confirmed through electron energy loss spectroscopic measurements. This work provides a feasible strategy for integrating 2DEG on a silicon wafer and other desired substrates, with potential significance for functional and flexible electronic devices.
Two-dimensional electron gas (2DEG) at the interface of amorphous Al2O3/SrTiO3 (aAO/STO) heterostruc-tures has received considerable attention owing to its convenience of fabrication and relatively high mobility. The integration of these 2DEG heterostructures on a silicon wafer is highly desired for electronic applications but remains challanging up to date. Here, conductive aAO/STO heterostructures have been synthesized on a silicon wafer via a growth-and-transfer method. A scanning transmission electron microscopy image shows flat and close contact between STO membranes and a Si wafer. Electron energy loss spectroscopic measurements reveal the interfacial Ti valence state evolution, which identifies the formation of 2D charge carriers confined at the interface of aAO/STO. This work provides a feasible strategy for the integration of 2DEG on a silicon wafer and other desired substrates for potential functional and flexible electronic devices.

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