4.7 Article

Logic Locking of Integrated Circuits Enabled by Nanoscale MoS2-Based Memtransistors

期刊

ACS APPLIED NANO MATERIALS
卷 5, 期 10, 页码 14447-14455

出版社

AMER CHEMICAL SOC
DOI: 10.1021/acsanm.2c02807

关键词

integrated circuits; two-dimensional material; logic locking; security; in-memory computing

资金

  1. National Science Foundation (NSF) through CAREER Award
  2. The Pennsylvania State University 2D Crystal Consortium-Materials Innovation Platform (2DCCMIP) under NSF cooperative agreement
  3. [DMR-2039351]
  4. [ECCS-2042154]

向作者/读者索取更多资源

With the globalization of the semiconductor chip manufacturing supply chain, intellectual property piracy and hardware security threats have become severe issues. This article introduces a new logic locking technique using two-dimensional nanoscale memtransistors for programmable logic gates, which have high efficiency and low energy consumption. The article also demonstrates the strong resilience of this technique against SAT attacks, thanks to the device-level logic locking capability of two-dimensional memtransistors. The importance of this technology is increasing for chip manufacturing companies.
With an ever-increasing globalization of the semiconductor chip manufacturing supply chain coupled with soaring complexity of modern-day integrated circuits (ICs), intellectual property (IP) piracy, reverse engineering, counterfeiting, and hardware trojan insertion have emerged as severe threats that have compromised the security of critical hardware components. Logic locking (LL) is an IP protection technique that can mitigate these threats by locking a given IC with a secret key. Earlier LL demonstrations based on traditional silicon complementary metal oxide-semiconductor (CMOS) technology and emerging memristors require significant hardware investment in the form of additional input gates and extensive CMOS peripherals, rendering them area-and energy-inefficient. In this article, we demonstrate multiple two-dimensional (2D) nanoscale memtransistor-based programmable logic gates such as AND, NAND, OR, XOR, and NOT gates, each of which can be locked/unlocked without requiring peripherals and at minuscule energy expenditure (<1 pJ). We also show that SAT-solver is unsuccessful in breaking into any of the ISCAS'85 benchmark circuits that utilize our LL scheme. The massive resilience to SAT-attack is attributed to the prowess of programmable 2D memtransistors which enable device-level LL of all the gates in each of the benchmark circuits. Given that 2D transistors are drawing increasing attention of chip manufacturing corporations like Intel, TSMC, etc., to replace and/or augment silicon at aggressively scaled technology nodes, our demonstration of area-and energy-efficient LL can be considered as a step toward the realization of secure ICs enabled by 2D nanoscale memtransistors.

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