期刊
ELECTRONICS
卷 11, 期 19, 页码 -出版社
MDPI
DOI: 10.3390/electronics11193072
关键词
analog-to-digital converter; noise-shaping; pipelined SAR ADC; pipelined noise-shaping SAR ADC; ring amplifier
资金
- National Research Foundation of Korea [2020R1A2C1099786]
- National Research Foundation of Korea [2020R1A2C1099786] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
This paper presents a pipelined noise-shaping SAR ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter.
This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The FoMS,SNDR is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.
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