Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells

For many decades, SRAM cell design with low power dissipation is the problem of interest for researchers due to its numerous applications in embedded systems. In this research work, a Bulk double gate FinFET based design of SRAM cell and performance analysis is carried out. Also, a comprehensive analysis is performed on FinFET and CMOS technology based SRAM cells. The novelty in the proposed work is, the designing of the 14 nm bulk double gate FinFET transistor using the FEM tool and eventually designing the SRAM cells. The designed bulk FinFET offers an I-DS of 3.5 mu A/mu m with HfO2 as dielectric material. By using this type of FinFET in SRAM cell design the leakage current is reduced significantly. The performance analysis on 6 T(T represents the number of transistors used in the design of SRAM cell), 7 T, 8 T and 9 T SRAM cells design with MOSFET and FinFET technologies is done in terms of leakage current, power dissipation and static noise margin. Compared with MOSFET, FinFET based SRAM cell offers low leakages especially 7 T SRAM cell has low leakage of 296.7 pW. The SRAM cells SNM value is also improved by 10 %.

Automated summary

This research work focuses on the design and performance analysis of a Bulk double gate FinFET based SRAM cell. The use of 14 nm bulk double gate FinFET transistors significantly reduces leakage current in SRAM cells. Performance analysis shows that FinFET based SRAM cells have lower leakage and improved SNM values compared to MOSFET based cells.