4.8 Article

Self-organization of an inhomogeneous memristive hardware for sequence learning

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NATURE COMMUNICATIONS
卷 13, 期 1, 页码 -

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NATURE PORTFOLIO
DOI: 10.1038/s41467-022-33476-6

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资金

  1. EU Horizon 2020 Memscales project [871371]
  2. SNSF grant SMALL [20CH21_18699]
  3. Toshiba corporation

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Learning plays a crucial role in creating intelligent machines. This study introduces MEMSORN, an adaptive hardware architecture that incorporates resistive memory (RRAM) to achieve self-organizing spiking recurrent neural network. The utilization of technologically plausible learning rules based on Hebbian and Homeostatic plasticity, derived from statistical measurements of fabricated RRAM-based neurons and synapses, improves the network accuracy by 30% in sequence learning tasks. Furthermore, the comparison with a fully-randomly-set-up spiking recurrent network demonstrates that self-organization can enhance the accuracy by over 15%.
Learning is a fundamental component of creating intelligent machines. Biological intelligence orchestrates synaptic and neuronal learning at multiple time scales to self-organize populations of neurons for solving complex tasks. Inspired by this, we design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorporates resistive memory (RRAM) in its synapses and neurons which configure their state based on Hebbian and Homeostatic plasticity respectively. For the first time, we derive these plasticity rules directly from the statistical measurements of our fabricated RRAM-based neurons and synapses. These technologically plausible learning rules exploit the intrinsic variability of the devices and improve the accuracy of the network on a sequence learning task by 30%. Finally, we compare the performance of MEMSORN to a fully-randomly-set-up spiking recurrent network on the same task, showing that self-organization improves the accuracy by more than 15%. This work demonstrates the importance of the device-circuit-algorithm co-design approach for implementing brain-inspired computing hardware.

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