A 20 Gbps PAM4 VCSEL driving ASIC for detector front-end readout

This paper presents the design and the test results of a 20 Gbps 4-level Pulse Amplitude Modulation (PAM4) Vertical Cavity Surface Emitting Laser (VCSEL) driving ASIC fabricated in a 55 nm CMOS technology for detector front-end readout. The PAM4 VCSEL driving ASIC consists of a Least Significant Bit (LSB) channel, a Most Significant Bit (MSB) channel and a novel PAM4-core output driver stage. This PAM4 VCSEL driving ASIC has been integrated in a customized optical module with the VCSEL array, and both the electrical function and the optical performance of the ASIC have been fully evaluated. The optical test results show that the Ratio Level Mismatch (RLM) of 20 Gbps eye diagram is 0.96, the Transmitter Dispersion Eye Closure Quaternary (TDECQ) is 0.63 dB, and the optical modulation amplitude is 761 mu W.

Automated summary

This paper presents the design and testing results of a 20 Gbps 4-level PAM4 VCSEL driving ASIC fabricated using 55 nm CMOS technology. The ASIC consists of an LSB channel, an MSB channel, and a novel PAM4-core output driver stage. It has been integrated in a customized optical module with the VCSEL array, and both its electrical function and optical performance have been fully evaluated.