Hardware implementation of a strong pseudorandom number generator based block-cipher system for color image encryption and decryption

This paper proposed a hardware architecture of a strong block-cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm is proposed to ensure high-level security and low computational complexity of image encryption. The algorithm performs image encryption mainly through three processes: pixel values hiding by applying the XOR operation with a key, pixel positions hiding by operating random permutation, and pixel substitution using the S-box method. To increase the complexity, R rounds of encryption could be accomplished in a loop. Then as a final step, using the Xilinx Vivado/system generator tool, the hardware cryptosystem is developed, implemented, and evaluated on an FPGA-Zynq evaluation board. According to the synthesis results, the suggested hardware system performs on a reduced FPGA area and gives a good frequency of 156.813 MHz with a high throughput of 20,072.064 Mbps. Several tools and tests utilizing various images are used to evaluate and analyze the hardware cryptosystem. The experimental results show that the hardware implementation has higher performance compared to other recent works.

Automated summary

This paper proposes a hardware architecture for a strong block cipher system dedicated to digital image encryption and decryption. It utilizes a pseudorandom number generator based on two 3D chaotic systems to generate strong keys, and employs a robust algorithm to ensure high security and low computational complexity. Through multiple processes, a high-performance encryption system is implemented on hardware.