A 12-Bit Current-Steering DAC With Unary-Splitting-Binary Segmented Architecture and Improved Decoding Circuit Topology

This article presents a three unary bits + five splitting bits + four binary bits segmented 500-MS/s current-steering digital-to-analog converter (DAC). The proposed splitting decoding method is between the unary decoding and binary decoding, in terms of number of switched elements. It can optimize the differential n o nlinearity and output glitches of DAC, with a more simplified circuit scale than unary decoding method. Due to the data-transmission topology, both the proposed thermometer and splitting decoders feature lower transistor count and occupy less area than other competitors. Their low latency accommodates to fast synchronization control of current source switches and its beneficial to the spurious-free dynamic range (SFDR) improvement of DAC. When implemented in a 0.1.8-mu m CMOS process, the 12-bit DAC occupies an active area of 536 mu m x 340 mu m, with the proposed decoders occupying only 28 mu m x 75 mu m. The DAC dissipates 17.20 mW at 500 MS/s with a 1.8-V analog supply and a 1.2-V digital supply. The differential and integral nonlinearities are measured to be 0.28 and 1.16 LSB, respectively. The DAC also features SFDRs of 68.83 and 62.06 dB for input signals of 6.34 and 239.74 MHz, respectively.

Automated summary

This article presents a DAC design with three unary bits, five splitting bits, and four binary bits, which optimizes the performance and reduces the area through decoding method and data-transmission topology.