Multilevel 3-D Device Simulation Approach Applied to Deeply Scaled Nanowire Field Effect Transistors

Three silicon nanowire (SiNW) field effect transistors (FETs) with 15-, 12.5- and 10.6-nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental I-D-V-G characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in k-space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed I-D-V-G characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations.

Automated summary

In this study, three silicon nanowire field effect transistors were simulated using hierarchical multilevel quantum and semiclassical models, and verified against experimental characteristics. The research demonstrates the significant impact of accurate parameterization of band structure and quantum confinement on the computed characteristics of nanoscaled devices.