期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 57, 期 9, 页码 2791-2801出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2022.3159569
关键词
Ash; Calibration; Capacitance; Switches; Voltage; Power demand; Interpolation; Analog-to-digital conversion; flash analog-to-digital converter (ADC); offset calibration; time-domain interpolation; time-interleaved; two-step flash ADC; voltage-to-time conversion
资金
- Samsung Research Funding Center of Samsung Electronics [SRFC-IT1502-04]
A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. The ADC shows improved power efficiency and area efficiency as well as input bandwidth. Advanced calibration techniques enhance gain and interpolation linearity. The prototype ADC demonstrates high performance and power efficiency.
A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm(2), including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.
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