期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 57, 期 10, 页码 2957-2968出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2022.3192903
关键词
Transistors; Costs; Internet of Things; MOSFET; Security; Circuit stability; Inverters; Area-efficient; cost-effective; differential nand; hardware security; Internet of Things (IoT); physically unclonable function (PUF); weak PUF
资金
- Basic Science Research Program through the National Research Foundation of Korea [2019R1A2C4070438, 2021R1A6A3A13046051, 2022R1A2B5B02002350]
- Samsung Electronics
- National Research Foundation of Korea [2022R1A2B5B02002350, 2021R1A6A3A13046051, 2019R1A2C4070438] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
This paper introduces a current-integration-based differential NAND-structured PUF, which achieves higher sensitivity to threshold voltage variation and more stable response generation compared to weak inversion operation, while maintaining faster speed.
A current-integration-based differential NAND-structured physically unclonable function (PUF) with 20F(2) area per bit is proposed for low-cost IoT security. Current integration scheme with a capacitor is adopted to generate a response bit by comparing the delay of capacitor charging through pair of selected MOSFET transistors. For area-efficient implementation, minimum-sized MOSFETs are selected from NAND-flash-like array structure. By operating selected MOSFET pairs in moderate inversion mode, higher sensitivity to threshold voltage (V-th) variation, and hence more stable response generation, is achieved while keeping it faster than weak inversion operation. A stabilization scheme based on current integration is proposed by discarding or remapping the transistor pairs that generate small charging delay difference. The proposed current-integration-based differential NAND-structured PUF (CI NAND-PUF) achieved high V/T variation tolerance of 0.145%/ 0.1 V and 0.120%/10 degrees C while limiting 20F(2)/bit area for 1-bit random response generation. With the proposed stabilization scheme, up to 11x and 7.7x BER improvement is achieved for trimming and remapping, respectively.
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