Physics-Based Compact Model of Current Stress-Induced Threshold Voltage Shift in Top-Gate Self-Aligned Amorphous InGaZnO Thin-Film Transistors

Threshold voltage shift (Delta V-T) under various current stress (CS) conditions need to be quantitatively studied in self-aligned top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Here, we propose a stretched-exponential function (SEF)-based Delta V-T model that can be applied to various combinations of V-GS and V-Ds. The proposed model indicates the characteristic electron trapping time constant ri is inversely proportional to (V-GS - V-T). In contrast, the time constant tau(2) is directly proportional to the square root of (V-Ds +V-bi), presumably due to the local donor creation by a lateral electric field. The proposed model was verified experimentally in various V-GS and V-Ds configurations. Further, it is confirmed that the lateral electric field dominantly influences donor creation near the drain.

Automated summary

In this study, the threshold voltage shift in self-aligned top-gate amorphous InGaZnO thin-film transistors under various current stress conditions was quantitatively studied. A stretched-exponential function-based model was proposed, which showed that the electron trapping time constant was inversely proportional to the difference between the gate-source voltage and the threshold voltage, and the time constant was directly proportional to the square root of the sum of the drain-source voltage and the built-in voltage, potentially due to the lateral electric field-induced local donor creation near the drain. The proposed model was experimentally verified and it was confirmed that the lateral electric field dominantly influenced donor creation near the drain.