Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SSth of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance G(m) at 5.5 K.

Automated summary

Fully silicided source/drain Si gate-all-around (GAA) nanowire p-FETs with nanowire diameter of 5 nm were fabricated and characterized from room temperature down to 5.5 K. The devices exhibited close to ideal transfer characteristics and sharp switching at both room temperature and 5.5 K, with improved transconductance at 5.5 K.