A simulated fabrication and characterization of a 65 nm floating-gate MOS transistor

The aim of this study was to virtual fabricate and characterize a Floating-gate MOS transistor of the 65 nm process. The fabrication process was designed and characterized using the TCAD Silvaco tools. In our work, a detailed flow and the parameters are proposed to virtual fabricate the complete Floating-gate MOS transistor, which has extraordinary performances. The MOS has a large timing win-dow of 4 V, a high gate capacitance ratio parameter of 0.645, and a high Write/Erase speed of 50 ms/70 ms. Interestingly, the results are obtained with a thin thickness of 9 nm of a tunnel oxide layer which is smaller than such layer in other works and low supply voltages in which the control gate, drain, and source voltage values are +/- 6 V, 1 V, and 1 V, respectively. In addition, our paper presents the effect of the control gate voltage on the performance of the device when it increases from 6 V to 18 V.(c) 2022 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Ain Shams Uni-versity. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/ by-nc-nd/4.0/).

Automated summary

The study aimed to virtually fabricate and characterize a 65 nm process Floating-gate MOS transistor. The proposed fabrication process and parameters were used to virtually fabricate the complete transistor with extraordinary performances. The results showed the characteristics of the device under a thin thickness of 9 nm tunnel oxide layer and low supply voltages.