Fully Parallel Proposal of Naive Bayes on FPGA

This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gate Array (FPGA) is presented and evaluated regarding the hardware area occupation, processing time (throughput), and dynamic power consumption. In addition, a comparative design analysis was carried out with state-of-the-art works, showing that the proposed implementation achieved a speedup of up to 10(4)x and power savings of up to 10(7)x-times while also reducing the hardware occupancy by up to 10(2)x-times fewer logic cells.

Automated summary

This work proposes a fully parallel hardware architecture for the Naive Bayes classifier and evaluates it on an FPGA. Experimental results show that the proposed implementation performs well in terms of speed and power consumption compared to other state-of-the-art works.