Nanoelectromechanical (NEM) Devices for Logic and Memory Applications

research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.

Automated summary

Research on NEM devices for logic and memory applications has been reviewed in the context of monolithic 3D (M3D) heterogeneous integration. The backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are detailed, and 65-nm process based M3D CMOS-NEM RL circuits are proposed. It is predicted that these proposed circuits will exhibit significantly higher chip density, operation frequency, and lower power consumption compared to CMOS-only circuits in tile-to-tile operation.