MESO-LUT: A design approach of look up tables based on MESO devices

The look-up-table (LUT) is widely used in the field of the field programmable gate arrays (FPGA), in which the high efficiencies of energy consumption, area, and speed are primarily concerned. In this paper, a new interconnected LUT structure constructed by the core element of the magnetoelectric spin-orbit logic (MESO) device is proposed. A SPICE model of a MESO-LUT circuit to achieve a two-input logic function is established by which the writing, reading and standby power consumptions are investigated. Comparing with the state-of-art LUT designs based on spin-orbit torque device, resistive switching memory and clockless spin-based LUT, the number of the auxiliary transistors of the proposed 6-input MESO-LUT respectively decreased similar to 13% , similar to 41% and similar to 81%,due to the property of representing the information by current direction which is promising in the future low power application scenario.

Automated summary

A new interconnected LUT structure based on MESO device is proposed in this study, showing promising prospects in future low power applications due to its property of representing information by current direction. Compared to other LUT designs, the number of auxiliary transistors in this structure is significantly reduced.