Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs

Static random access memory (SRAM) based field-programmable gate array (FPGA) is currently facing challenges of high leakage power and limited capacity. Replacing SRAM in FPGA with emerging nonvolatile memory (NVM) has become an effective way to solve this issue. While enjoying the advantages of NVM in power consumption and integration, nonvolatile FPGA platform is also plagued by lifetime problem. Among all components, block random access memory (BRAM) has the severest endurance problem. The state-of-the-art wear leveling strategies for NVM-based BRAMs rely heavily on static analysis. However, the static analysis would not be accurate enough for application with multiple runtime working patterns. In this article, we propose a pattern-aware wear leveling mechanism. It can improve lifetime through adaptive reconfiguration without static analysis. Evaluation shows that our mechanism can achieve 120% higher lifetime improvement with 4% performance overhead than existing performance-aware wear leveling strategy (Huai et al., 2019).

Automated summary

This article introduces a pattern-aware wear leveling mechanism to improve the lifetime problem in nonvolatile FPGA platforms. Compared to existing static analysis methods, this mechanism improves lifetime through adaptive reconfiguration, with higher lifetime improvement and lower performance overhead.