期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 69, 期 7, 页码 2885-2892出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2022.3165469
关键词
Field programmable gate arrays; Hardware; Chaotic communication; Signal processing algorithms; Computer architecture; Adders; Trajectory; Chaotic systems; CORDIC; FPGA; reconfigurable; transcendental
资金
- Science, Technology, and Innovation Funding Authority (STIFA) [38161]
This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. It demonstrates efficient hardware utilization and suitability for potential applications.
Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据