Vertical ferroelectric thin-film transistor array with a 10-nm gate length for high-density three-dimensional memory applications

Hafnia-based ferroelectric thin-film transistors (FeTFTs) are regarded as promising candidates for future nonvolatile memory devices owing to their low power consumption, high operational speed, and complementary metal-oxide-semiconductor compatibility. However, the scalability of hafnia-based materials and the feasibility of three-dimensional (3D) device fabrication should be confirmed for ultrahigh-density memory applications. In this work, we demonstrate that FeTFTs can be scaled down to a 10-nm dimension using the vertical structure with a hafnia-based ferroelectric gate insulating layer and an oxide semiconductor channel. We show that such vertical FeTFTs can be operated with an effective device size of 0.005 mu m(2), a fast operation speed of < 100 ns, and a high endurance of 10(8) cycles. Additionally, the string-level NAND operation is demonstrated using the vertical FeTFT array. Finally, device simulation confirms the possibility of ultrahigh-density 3D ferroelectric NAND with 200 gate stacks. These results demonstrate the ultrahigh scalability of FeTFTs as a promising candidate for next-generation 3D nonvolatile memory. Published under an exclusive license by AIP Publishing.

Automated summary

This study demonstrates the scalability of Hafnia-based ferroelectric thin-film transistors (FeTFTs) to a 10-nm dimension and showcases their high scalability and suitability for ultrahigh-density memory applications.