A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications

Driven by Moore's law, the chip design complexity is steadily increasing. Electronic DesignAutomation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks (GNNs) are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate Register Transfer Levels, and netlists. In this article, we present a comprehensive review of the existing works linking the EDA flow for chip design and GNNs. We map those works to a design pipeline by defining graphs, tasks, and model types. Furthermore, we analyze their practical implications and outcomes. We conclude by summarizing challenges faced when applying GNNs within the EDA design flow.

Automated summary

Driven by Moore's law, chip design complexity is increasing steadily. Electronic Design Automation (EDA) can handle the challenges of very large-scale integration and ensure scalability, reliability, and timely market introduction. However, EDA approaches are time and resource demanding, often without guaranteeing optimal solutions. To address this, Machine Learning (ML) has been integrated into various stages of the design flow, including placement and routing. Graph Neural Networks (GNNs) provide an opportunity to directly solve EDA problems using graph structures. This article comprehensively reviews the existing works linking EDA flow and GNNs, mapping them to a design pipeline, analyzing their practical implications, and summarizing the challenges faced when applying GNNs in the EDA design flow.