High coherence and low cross-talk in a tileable 3D integrated superconducting circuit architecture

We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T-1 = 149(38) mu s, pure echoed dephasing times T-phi,T-e = 189(34) mu s, and single-qubit gate fidelities F= 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.

Automated summary

This paper reports high qubit coherence, low cross-talk, and single-qubit gate errors in a superconducting circuit architecture that can be tiled into a two-dimensional lattice of qubits. The architecture integrates an inductively shunted cavity enclosure with non-galvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. Experimental results demonstrate the feasibility of the design, and simulations predict that the enclosed qubits will maintain a clean electromagnetic environment at arbitrary scale.