4.7 Article

Analytical Expressions for Inductances of 3-D Air-Core Inductors for Integrated Power Supply

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2021.3077203

关键词

3-D solenoid inductor; 3-D toroidal inductor; air core; inductance model; loop inductance; mutual inductance; partial inductance; power supply in package (PSiP); power supply on chip (PwrSoC); self-inductance; through silicon via (TSV)

资金

  1. Science Foundation Ireland (SFI) [15/IA/3180]
  2. Science Foundation Ireland (SFI) [15/IA/3180] Funding Source: Science Foundation Ireland (SFI)

向作者/读者索取更多资源

This work presents analytical expressions for the dc inductance of 3-D air-core inductors with different cross-sectional pillars and discusses the effects of high frequency on inductance. The proposed analytical models show good agreement with numerical analysis and measurement results, providing accurate predictions for various inductor structures.
This work presents analytical expressions for the dc inductance of 3-D air-core inductors with circular cross-sectional pillars (CCSPs) and rectangular cross-sectional pillars (RCSPs). We consider the following four types of inductor structures: 1) a toroid with CCSP; 2) a toroid with RCSP; 3) a solenoid with RCSP; and 4) a solenoid with CCSP. For each type, a unique analytical model is developed for obtaining dc inductance. High-frequency (1-100 MHz) effects on inductance are also discussed. The inductance values predicted by the proposed analytical models of the first three types of inductor structures are in an acceptable agreement with numerical finite-element analysis (FEA) solutions, where the maximum difference is 7.3%. Also, our analytical model for the fourth-type inductor reduces the error, when correlated with FEA inductance value, up to 6x compared with previously published models. A comparison of results using the proposed analytical expressions with published measured values as well as our measurement data demonstrates the error ranging from 0.5% to 16.2%, while conventional formulas show errors of up to 143%. The results of the proposed models could serve as a good initial estimate for power supply-on-chip (PwrSoC) and power supply in package (PSiP) applications.

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