Hidden Inverses: Coherent Error Cancellation at the Circuit Level

Coherent gate errors are a concern in many proposed quantum-computing architectures. Here, we show that certain coherent errors can be reduced by a local optimization that chooses between two forms of the same Hermitian and unitary quantum gate. We refer to this method as hidden inverses, and it relies on constructing the same gate from either one sequence of physical operations or the inverted sequence of inverted operations. We use parity-controlled Z rotations as our model circuit and numerically show the utility of hidden inverses as a function of circuit width n. We experimentally demonstrate the effectiveness for n = 2 and n = 4 qubits in a trapped-ion quantum computer. We numerically compare the method to other gate-level compilations for reducing coherent errors.

Automated summary

In this paper, a method for reducing coherent errors by using hidden inverses is demonstrated. The effectiveness of this method is numerically simulated and experimentally validated on a trapped-ion quantum computer.