Optimal Design and Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor

Tunneling field effect transistors (TFETs) have been proposed as switches for low-power integrated circuits. A negative-capacitance vertical-tunnel FET that improves vertical tunnelling over corner tunnelling. This is due to the fact that when there is negative capacitance, a stronger vertical electric field is formed. The device can be altered to operate in the TFET or MOSFET modes and tweaked to act as an n-type or p-type FET by changing the electrostatic doping utilising multiple gates. Tunnel FET is a device that has a lot of potential for replacing MOSFETs and their shortcomings (TFET). Applying the appropriate gate bias turns ON this simple gated P I N diode. Because of the Band To Band Tunneling (BTBT) concept underpinning these Tunneling FETs, a current can flow from the p-valence region's band to the intrinsic area's conduction band. Low-power applications can benefit from this design because of the reduced OFF-state leakage current (I-OFF). As a result, the proposed study makes use of a novel vertically stacked TFET structure that combines the benefits of uniformly doped junctionless transistors with the tunnelling effect. A 2D TCAD simulation programme is used to simulate and confirm the analytical model findings. As a result of the findings, the device's surface potential, electric field, and threshold voltage have all been greatly improved.

Automated summary

Tunneling field effect transistors (TFETs) have the potential to replace MOSFETs as low-power switches. This study proposes a novel vertically stacked TFET structure that combines the benefits of uniformly doped junctionless transistors with tunneling effect. The device can be operated in TFET or MOSFET modes and can be altered to act as an n-type or p-type FET by changing the gate bias.