Geometrical Variability Impact on the Performance of Sub-3 nm Gate-All-Around Stacked Nanosheet FET

To meet the scaling targets and continue with Moore's Law, the transition from FinFET to Gate-All-Around (GAA) nanosheet Field Effect Transistors (FETs) is the necessity for low-power to high-performance applications in upcoming nodes. In this work, we benchmark nanosheet FET against FinFET of comparable dimensions. Due to increased effective width, stacked nanosheet FET offers improved DC and analog/RF performance over multi-fin FinFET. The impact of geometrical parameter variations on the performance of stacked Si nanosheet FET is investigated for sub-3 nm technology node. We have considered nanosheet thickness (NST), nanosheet width (NSW), number of channels and oxide thickness (t(ox)) as the sources of variability. The simulation carried out on Genius TCAD device simulator reports that higher NST, higher NSW, more number of channels and thinner oxide results in improved device driving capability, ON-current (I-on), transconductance (g(m)), intrinsic delay and cut-off frequency (f(t)). OFF-current (I-off), ON-current to OFF-current ratio (I-on/I-off), immunity against short channel effects (SCEs) and gate capacitance (C-gg) can be improved using lower NST, lower NSW, lesser number of channels and thinner oxide. However, threshold voltage (V-th) roll-off is more pronounced for thinner and narrower sheets with a thin oxide.

Automated summary

To meet the scaling targets and continue with Moore's Law, the transition from FinFET to Gate-All-Around (GAA) nanosheet Field Effect Transistors (FETs) is necessary. This work benchmarks nanosheet FET against FinFET and finds that stacked nanosheet FET offers improved performance. The study investigates the impact of geometrical parameter variations on the performance of stacked nanosheet FET and identifies the factors that contribute to better driving capability, current, and delay.