Design and Performance Assessment of HfO2/SiO2 Gate Stacked Ge/Si Heterojunction TFET on SELBOX Substrate (GSHJ-STFET)

In this work, gate stacked hetero-junction TFET on SELBOX substrate (GSHJ-STFET) has been proposed. Comparative electrical performance analysis has been performed between proposed GSHJ-STFET structure with fully depleted SOITFET. The optimized proposed TFET structure has been explored for DC, and RF/analog performance matrix such as I-ON, I-OFF, I-ON/I-OFF ratio, subthreshold swing (SS), transconductance (g(m)), threshold voltage (V-T), cut-off frequency (f(T)), transit time (t), gain bandwidth product (GWB), maximum oscillating frequency (f(MAX)), TGF, and TFP. It has been found that proposed TFET with SELBOX shows better static performance compared to conventional fully depleted SOI-TFET (FD-SOITFET). Further, the temperature reliability analysis has been extensively investigated for both conventional fully depleted SOI TFET and proposed TFET, respectively.

Automated summary

In this work, a gate stacked hetero-junction TFET on SELBOX substrate (GSHJ-STFET) is proposed and compared with fully depleted SOITFET in terms of electrical performance. The optimized TFET structure shows better static performance compared to conventional fully depleted SOI-TFET. Furthermore, the temperature reliability of both structures is extensively investigated.